1. Field of the Invention
The present invention relates to the field of latchup in integrated circuits, and in particular, to an overvoltage containment circuit for protecting integrated semiconductor devices from input currents that may cause latchup.
2. Related Art
Conventional complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) are inherently susceptible to latchup due to the close proximity of the n-channel and p-channel transistors to one another. Together with the semiconductor material forming the substrate of the integrated CMOS device, the diffused regions within the device can form parasitic transistors.
Latchup is a high current state accompanied by a collapsing or low-voltage condition established by a very low resistance path between the VDD voltage supply and circuit ground. When the parasitic transistors are biased appropriately, the transistors can effectively short the supply voltage to ground potential in latchup mode, causing a very large current to flow through the IC. This high current state can be triggered by application of a radiation transient or certain electrical excitations. At best, latchup only results in a disruption of the logic processes conducted by the CMOS device and, at worst, it results in destruction of the device. Furthermore, latchup continues to be an increasing problem due to the decrease in device dimensions and use of non-epitaxial substrates in integrated circuit fabrication to reduce crosstalk and cost.
FIG. 1a is a simplified cross-section of a conventional p-well n-substrate CMOS inverter circuit 100. A corresponding schematic diagram of the parasitic transistor configuration is shown in FIG. 1b, where bipolar transistor Q1 is the parasitic lateral p-n-p transistor, and bipolar transistor Q2 is the parasitic vertical n-p-n transistor. The emitter of the lateral transistor Q1 is the p+ source 113 and/or drain 115, while its base is the n-substrate 103 and its collector is the p-well 101. The n+ source 111 and/or drain 109 comprises the emitter of the vertical transistor Q2, while the p-well 101 forms its base and the n-substrate 103 its collector. Voltage supply VDD is applied at terminal 105 and circuit ground GND is applied at terminal 107. V.sub.IN and V.sub.OUT are the input and output terminals, respectively. The n+ source/drain regions 109, 111 comprise an N-channel MOS transistor while the p+ drain/source regions 113, 115 comprise the P-channel MOS transistor. The p+ region 117 forms an ohmic substrate 103 contact and n+ region 119 forms an ohmic p-well 101 contact. As shown in the schematic circuit diagram of FIG. 1b, currents I1 and I2 are the external trigger currents in the n-substrate 103 and p-well 101, respectively, which initiate transient latchup.
In the presence of external triggering currents I1, I2, such as a voltage overshoot, the emitter-base junction of a parasitic bipolar transistor Q1, Q2 becomes forward-biased. Typically, once this forward-biasing occurs, the number of minority carriers injected from the emitter of the bipolar transistor Q1, Q2 that reach the collector is reduced due to the parasitic minority carrier flow from the emitter directly into the substrate 103. This current flow into the substrate 103 causes the circuit to malfunction.
Transient overshoot voltages are a particular problem at the outputs of MOS driver circuits since impedance mismatches at the far ends of transmission lines result in reflections that return to the driver output node. Furthermore, overshoots are also common at input/output (I/O) device nodes where signals tend to be noisy. Thus, use of latchup preventive designs are very important at the input and output circuitry of CMOS chips.
Latchup may be prevented by holding the voltage of the substrate close to the voltage level of one of the supply voltage levels which may comprise, for example, ground potential. This may be accomplished by providing low resistance current paths to ground potential which are electronically coupled to the semiconductor substrate material. One method used to accomplish this in conventional devices is the use of a low resistance substrate having an epitaxial layer of semiconductor material formed outwardly from the low resistance layer. The use of epitaxial substrates is highly effective in preventing latchup but is a very expensive solution and is becoming more and more expensive as semiconductor wafer diameters increase. An alternate solution is the use of low resistance guard rings surrounding the n-channel device within the integrated CMOS structure constructed on a p-type semiconductor substrate. This solution is commonly used in input/output devices where the output pins of the integrated devices are susceptible to dramatic fluctuations due to external systems. The use of guard rings is effective but is, once again, very expensive in terms of the amount of surface area that must be dedicated to the guard rings.
Several other conventional methods have been used to prevent potential latchup in integrated circuits, such as the use of dielectric isolation to decouple the bipolar interaction with the MOS circuit. This method, while providing significant suppression of latchup, involves complicated processing, which makes it impractical. Another method of suppressing latchup is reducing carrier lifetimes around the regions where bipolar action takes place. This processing scheme involves ion implanting a minority carrier lifetime reducer ("MCLR") impurity into a CMOS integrated circuit so that the impurity is located in the active region of the parasitic bipolar transistor elements.
Although these conventional methods reduce latchup to a certain degree, they require the use of expensive epitaxial layers, complicated processing, or the dedication of semiconductor surface area to guard ring structures.
Thus, a need exists to minimize the current escaping into the non-epitaxial substrate, which in turn, improves latchup results.